How can a logic packed array be driven to X (don't care) from within a uvm sequence?

UVM
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1

Hi

In a system verilog +uvm testbench, a dut bus is driven from the verification environment by a “bus model” of type logic packed array:


logic [dim:0] dut_bus_connection;

How can this be driven to x from a sequence?

Simply assigning x to each of the bus positions in a foreach loop:


 foreach (dut_bus_connection[i]) dut_bus_connection  =x;

,drives the bus to 0, not x.

2

In reply to Brass:

There is not enough information to know what might be going wrong. You need to make sure all the variables that this variable goes through are also 4-state (i.e. drier and interface).

Also you could have just written

dut_bus_connection  = 'x;

without using a foreach loop.

3

In reply to dave_59:

Hi Dave

Thanks for suggested fix: the bottleneck was a return type of a post processing function which returned type bit.

Thank you