Hi
In a system verilog +uvm testbench, a dut bus is driven from the verification environment by a "bus model" of type logic packed array:
logic [dim:0] dut_bus_connection;
How can this be driven to x from a sequence?
Simply assigning x to each of the bus positions in a foreach loop:
foreach (dut_bus_connection[i]) dut_bus_connection =x;
,drives the bus to 0, not x.
