How are two tops (hvl_top and hdl_top) run in one simulation?

UVM
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1

Hi Forum,

I have a general “how’s it work question”

I see some testbench environments use an hdl_top and an hvl_top concept. This appears to be intended to separate synthesizable/emulatable code from non emulatable code…

These appear to be two separate and disconnected (one doesn’t invoke the other) top modules.

Questions:

  1. I’ve only seen simulator command line parameters specify a single top module, not two. Is it common to provide the simulator with two, top modules that it will run simultaneously, or is one invoking the other somehow that I don’t understand?
  2. I noticed an example (UVMF) where the two top modules were passed as parameters to an optimization step. Is that how the simulator starts both of them?

Note: My simulator user/reference guides don’t seem to describe dual top scenarios, thus the reason for my question.

Thanks for your help, I appreciate it.
Brian

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In reply to jnbkeller:

A simulation can have many top level modules. Modules have initial and always blocks running as concurrent processes; it does not matter what the hierarchical relationship between the modules is.

Tools have different compilation flows to figure out which are the top-level modules. This Mentor/Siemens EDA sponsored public forum is not for discussing tool specific usage or issues. Please read your tool’s user manual (I’m sure the info is there somewhere) or contact your tool vendor directly for support.

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In reply to dave_59:

Thanks Dave. So it sounds like multiple top modules must be specified to the simulator when it’s invoked somehow (simulator specific, for me to figure out).

Thanks for your help,
Brian