Hierarchy of files in Systemverilog Package

UVM
,
1

Hello all,

I need help in knowing the correct hierarchy of files in system verilog package. My scenario is:

  1. one.svh file contains ten “.sv” files.

  2. two.svh file contains twelve “.sv” files.

  3. Two interface is there.

  4. One top.sv file.

  5. pack.sv package is there.

    My doubt is what should be the correct order of files in pack.sv package. My package looks like: Both interafce and top file is in two.svh header file.

 `include "uvm_macros.svh"
   package pack;
    import uvm_pkg::*;

     `include "one.svh"
     `include "two.svh" 
   endpackage

It is giving error:

1. near "interafce[1]": syntax error, unexpected IDENTIFIER, expecting class.
2. near "module[1]": syntax error, unexpected module, expecting class.

Please help and suggest in this regard.

Regards
Sunil

2

In reply to sunils:

Static constructs like modules or interfaces provide a local namespace to their declarations. Identifiers declared in these constructs are local to them and do not conflict with other declarations. Packages are providing also a namespace. For this reason it is not allowed to have modules, interfaces, programs and checkers in packages.
See chapter 3.9 Packages in the SV standard (2012).