Hierarchical reference name component lookup failed for 'uvm_test_top'

UVM
,
1

Trying to get a component from hierarchical reference name instead uvm_top.find()

    if(!$cast(env_s, uvm_top.find("uvm_test_top.env_o"))) `uvm_error(get_name(), "env_o is not found");
    Aseq.start(env_s.v_seqr.seqr_A);

So I checked UVM testbench topology:

------------------------------------------------------------
Name                       Type                    Size  Value
--------------------------------------------------------------
uvm_test_top               base_test               -     @1849
  env_o                    env                     -     @1916
    agt_A                  core_A_agent            -     @1948
      drv_A                core_A_driver           -     @2666
        rsp_port           uvm_analysis_port       -     @2770
        seq_item_port      uvm_seq_item_pull_port  -     @2718
      seqr_A               core_A_sequencer        -     @2803
        rsp_export         uvm_analysis_export     -     @2862
        seq_item_export    uvm_seq_item_pull_imp   -     @3422
        arbitration_queue  array                   0     -    
        lock_queue         array                   0     -    
        num_last_reqs      integral                32    'd1  
        num_last_rsps      integral                32    'd1  
    agt_B                  core_B_agent            -     @1979
      drv_B                core_B_driver           -     @3473
        rsp_port           uvm_analysis_port       -     @3574
        seq_item_port      uvm_seq_item_pull_port  -     @3525
      seqr_B               core_B_sequencer        -     @3605
        rsp_export         uvm_analysis_export     -     @3663
        seq_item_export    uvm_seq_item_pull_imp   -     @4215
        arbitration_queue  array                   0     -    
        lock_queue         array                   0     -    
        num_last_reqs      integral                32    'd1  
        num_last_rsps      integral                32    'd1  
    v_seqr                 virtual_sequencer       -     @2010
      rsp_export           uvm_analysis_export     -     @2071
      seq_item_export      uvm_seq_item_pull_imp   -     @2633
      arbitration_queue    array                   0     -    
      lock_queue           array                   0     -    
      num_last_reqs        integral                32    'd1  
      num_last_rsps        integral                32    'd1  
--------------------------------------------------------------

When I ran with uvm_test_top.env_o.v_seqr.seqr_A as the below I got the error message.
How do I correctly get a component from hierarchical name?

    //if(!$cast(env_s, uvm_top.find("uvm_test_top.env_o"))) `uvm_error(get_name(), "env_o is not found");
    //Aseq.start(env_s.v_seqr.seqr_A);

    Aseq.start(uvm_test_top.env_o.v_seqr.seqr_A);

** Error (suppressible): sequence.sv(63): (vopt-7063) Failed to find ‘uvm_test_top’ in hierarchical name ‘$root.uvm_test_top.env_o.v_seqr.seqr_A’.

Region: testbench_sv_unit.virtual_seq.

For your understand With Virtual Sequnce & virtual seqcr (Not p_se(1) - EDA Playground I implemented it.

2

In reply to UVM_LOVE:

“uvm_test_top” is not the name of a variable; it is the string name given to the uvm_test constructed by calling run_test. It is one (usually the only one) of the child components of uvm_top.

3

In reply to dave_59:

 if(!$cast(env_s, uvm_top.find("uvm_test_top.env_o"))) `uvm_error(get_name(), "env_o is not found");

If the cast succeeds, can I know where env_s has the hierarchical reference path?

4

In reply to UVM_LOVE:

env_s.get_full_name()
5

In reply to dave_59:

If it is only a string name, how can we reference/read/write a variable to/from a component?

For example, in my testcase, I would like to dynamically change the value of a variable.
If uvm_test_top is not the name of uvm_test instance variable, then this code below will not work. So how can I set the variable without using uvm_config_db?


// From testcase
uvm_test_top.env_o.config.varA = 10;
6

In reply to Reuben:

I do not understand your question. Your “testcase” has the env_o variable in it. There is no need to get the name of the test.

7

In reply to dave_59:

I mean from a sequence, this below will not work:


// From sequence
uvm_test_top.env_o.config.varA = 10;

So how can I set varA from the sequence?

I tried passing the handle of the parent but it is saying a compile error that env_o is not an item of the class. Here’s what I did:


// From my testcase, I pass the handle of the testcase to the sequence.
// In main_phase() and after creating vseq
// vseq is extended from base sequence
vseq.parent_handle = this;



// From base sequence
uvm_component parent_handle;

// Then from a certain virtual function() of the base sequence
if(parent_handle != null) begin
  parent_handle.env_o.config.varA = 10;  // Causing compile error
end

I used parent_handle.get_children() to see if env_o is a child of parent_handle, and it is reporting that env_o is its child. So I don’t know why it is causing a compile error saying that env_o is not an item of the class. I double-checked many times that env_o is instantiated in my base test class. So any testcase extended from the base class should get this env_o.

8

In reply to Reuben:

Your problem is that parent_handle is a uvm_component and does not contain env_o—base_test_class does. You wound need to downcast parent_handle to a base_test_class variable using a dynamic $cast.

9

In reply to dave_59:

I thought the OOP concept of polymorphism will allow an object with a parent data type to be changed as the extended data type, by just passing the handle.

Anyway, I will check. I might be missing a basic and important concept of polymorphism here.

10

In reply to Reuben:

You need to understand the difference between class objects, class types, and and class variables. The class type of the class variable determines what members of the class object you can reference regardless of what object handle is stored in the variable. parent_handle cannot reference identifiers that are not part of its type.

See my SystemVerilog OOP for UVM course.