Hiding print of certain components in Topology

UVM
,
1

Hi all ,

I see that uvm_component has property " bit print_enabled = 1 ; " ( public )

When set to 0 by user , the component is skipped from print in Topology .


class env extends uvm_component;
 `uvm_component_utils(env)
 // Both acomp and bcomp extend uvm_component 
 acomp acomp_h[4]; 
 bcomp bcomp_h;

 function new(string name, uvm_component parent=null);
   super.new(name,parent);
 endfunction
 
 virtual function void build_phase(uvm_phase phase);
  
   foreach(acomp_h[i])
    begin
	 acomp_h[i] = new($sformatf("acomp_h%0d",i),this);  
    end
     bcomp_h = new("bcomp_h",this);
  
  
   foreach(acomp_h[i])
    begin
     acomp_h[i].print_enabled = 0 ;  
    end 
     
     bcomp_h.print_enabled = 0 ;   
  
  endfunction

 virtual function void start_of_simulation_phase(uvm_phase phase);
   uvm_top.print_topology();
 endfunction

 
endclass

 initial begin 
 
 run_test("env"); // env would be uvm_test_top

 end

Gives Output ::

UVM_INFO @ 0: reporter [RNTST] Running test env…
UVM_INFO @ 0: reporter [UVMTOP] UVM testbench topology:

Name Type Size Value

uvm_test_top env - @454

I observe that component acomp and bcomp don’t get printed .

Consider a VIP where it doesn’t want its customers to know the full Topology of its product , if they were to use this approach the end user can always know about the Topology via explicitly setting the property to 1 again !.

[Q] So is there any other way to hide the Topology from user ?

Thanks ,
TC

2

In reply to TC_2017:

There are other ways of finding out the topology without using the printer routines. This bit was put in to hide trivial things like TLM ports, but I don’t think it was ever used. IEEE 1800.2 has removed this field from the LRM.

If your VIP is encrypted, there’s very little information you can get from knowing the topology.