Help with following Compilation Issue

UVM
,
1

I am facing a compilation issue ::


Error-[SE] Syntax error
  Following verilog source has syntax error :
        variable type is not user defined type
  "<ABSOLUTE_PATH_OF_RAL_regdef.svh FILE>",
  37: token is 'custom_regs'                                                                                      
     rand gen3_mphy_integ_t   custom_regs  ;

I have following code ::


class TOP_BLOCK extends uvm_reg_block ; // TOP LEVEL REGBLOCK
....          // Random handle to sub reg_blocks 
rand gen3_mphy_integ_t   custom_regs  ;  // Issue here

A handle name is user defined so I am unable to get the issue .

I compile the file containing declaration for gen3_mphy_integ_t ( reg_block ) prior to this TOP_BLOCK

2

In reply to MICRO_91:

All class-based stuff should be contained in a package in imported when you want to use it. This is different what we are doing with the satic constructs.

You should put your taype declartion gen3_mphy_integ_t into a package, compile this package prior to compiling the other code and importing the type package in your code.