In reply to haykp:
Hi Hayk,
I wrote pyuvm as a Python implementation of the UVM. So the UVM remains with all its sequences, tlm_fifos, ports, exports, etc. I simplified where I could to take advantage of the lack of strong typing in Python.
So its not a replacement for UVM, just another approach.
That said I can't definitively answer your questions because its so new. That said here are my answers.
Can anyone please do some experience sharing. Mostly I want to know
1) is this flow scalable for big designs
I see no reason that it would not be. One would compile the RTL once and then use the Python to create stimulus and check results. I suspect most of the time in a large design would be spent in the RTL simulation, but I haven't tested that.
2) Is it easy to debug complex DUT bugs using this flow
This is more a matter of using a tool such as Visualizer that captures all the signal
behavior in a simulation and lets you walk back through it like using a DVR.
3) Has anyone experience working with the flow to verify complex protocols such as PCIe
Nope.I released it three weeks ago
4) Why vendors do not support this flow?
Why do you say this? It works with all simulators.
5) What are drawbacks of this flow?
I don't understand how to link the testbench into a Python debugger. So right now the drawback is in debugging the testbench
I hope this helps.
Ray
