UVM Factory

UVM
,
1

Hi all ,

Last few days I went through various articles / papers / UVM code study on UVM Factory and Parameterized Tests .
Have a list of questions ::

(1) String N Type based Factory ::

 **run_test()  requires  test  to  be  registered  with  string - based factory ( internally it calls  factory.create_component_by_name )**

(i) I believe since run-time arguments ( via +UVM_TESTNAME=test ) are string literals , run_test() requires string - based factory .
[Q1] Am I correct with this or am I missing out on something else too ?

(ii) [Q2] Is string-based factory used in run_test() only or are there other areas where string-based factory is used ?

(2) Macro `uvm_component_param_utils doesn’t provide 2nd string argument to specialization of uvm_component_registry class .
It’s left to the user to provide 2nd argument explicitly

  **[Q3] Is  this  because  the  parameterized  component  could  have  N  parameters  associated  with it ? .
     So  there is  no  way  a  macro  would  know  how  many   parameters  are  associated  with  the  class**

(3) Factory registration is done via uvm_object_wrapper ( proxy class ) where the actual object is handle to
uvm_component_registry N uvm_object_registry .

 So  via  call  to  run_test()  the  appropriate  string  based  lookup  is  done  and  the  precise  Test Top  is  instantiated . 
 Similarly  via  calls  to   type_id::create()  Type-based  factory  is  used  and  the  appropriate  component / object  is  created .

 My  question  is  related  to  following  line  from  UVM  LRM  8.2.3  about  uvm_component_registry  ::

  **"Without  it  registration  would  require  an  instance  of  the  object  itself "**  
   
 **[Q4] What  does  the  above  line  mean  ??**
2

In reply to TC_2017:

If you want to select a test either with the argument to run_test() or the switch +UVM_TESTNAME, you need a fixed string to be registered with the factory. That fixed string has to be compiled into the design, and all the variations of that string have to be registered so they can be selected at run-time. But there is no requirement to use either as long as there is at least one uvm_component constructed before calling run_test(). The problem with the macros and parameterization is that macros get expanded into text before any SystemVerilog code gets parsed, so they could only register one set of parameterizations (their defaults) and one string with the factory.

You might want to read this about alternatives to the factory macros:

And this about how registration and object proxies work: