Expecting a right bracket error

UVM
1

Dear All,

I’m trying to make a tiny simple example of systemverilog array as the below,


module test();
  import uvm_pkg::*;
  `include "uvm_macros.svh"
  `include "uart_ctrl_regs.sv"

class test extends uvm_test;
  uart_ctrl_reg_model_c reg_model;
  uvm_reg regs[$];

  function void build();
    uvm_reg::include_coverage("*", UVM_CVR_ALL);
    reg_model=uart_ctrl_reg_model_c::type_id::create("reg_model", this);
    reg_model.build();
  endfunction

  task run();
    reg_model.reset();
    foreach(regs[$]) begin
    `uvm_info(get_type_name(), $psprintf("TEST = %s" , regs.get_name ), UVM_LOW)
    end
  endtask


  `uvm_component_utils(test)
  function new(string name, uvm_component parent);
    super.new(name,parent);
  endfunction
endclass
  initial run_test("test");
endmodule


class uart_ctrl_reg_model_c extends uvm_reg_block;
  virtual function void build();
  endfunction
  `uvm_object_utils(uart_ctrl_reg_model_c)
  function new(input string name="unnamed-uart_ctrl_reg_model_c");
    super.new(name, UVM_NO_COVERAGE);
  endfunction
endclass : uart_ctrl_reg_model_c

But I can’t understand the compile error message


    foreach(regs[$]) begin
                 |
ncvlog: *E,EXPRBK (testbench.sv,20|17): expecting a right bracket (']') [SystemVerilog foreach].

Could you please help me to understand the problem about why does it make such as error message?

EDA PLAYGROUND…

2

In reply to UVM_LOVE:

Syntax errors in Verilog can be very challenging and other tools might be better at explaining the problem based on their experience with the issue. The key point is ‘$’ is not valid to be where you have placed it.

The correct use of foreach is

 foreach(regs[index_variable]) begin
    `uvm_info(get_type_name(), $psprintf("TEST = %s" , regs[index_variable].get_name ), UVM_LOW)
    end