Ending a Test in Uvm

UVM
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Hi all,

I had a doubt in an example given in verification guide website.

EXAMPLE CODE

In the above example there is a forever loop in mem_driver run phase task. if its forever then how does it end doesn’t it get stuck.

I thought like in mem_sequence there are 2 packets generated therefore in driver also we need to get only 2 times. isn’t it right?

I am running mem_wr_rd_test and i changed sequence to mem_sequence in mem_wr_rd_test.
Thank you

2

In reply to sasi_8985:

You can read about how the UVM implements end-of-test on the Verification Academy