End of simulation criteria

UVM
1

Hi,

I have an issue with regards to getting a timeout to work for RTL hangs. I have implemented a small counter in the interface which on every posdege of clk, resets to max_timeout value upon reset or if it detects a output valid, otherwise decrements. In my test base. I have a task as below:

task check_end_of_simulation(int unsigned scenario_count);
     // Check whether it is okay to end the simulation
      fork
        begin
          wait(scenario_count == m_env.m_sys_mon.rsp_q.size());
          `uvm_info({get_type_name(), ":run"},"All the responses received. Hence terminating the test",UVM_MEDIUM) 
        end
        begin
          wait(inf.count == 0);
          `uvm_error({get_type_name(), ":run"},"Timed out. Hence terminating the test")
        end
      join_any

  endtask: check_end_of_simulation

and in every test I have something like:

 
   // Raise objection
   // randomize the vseq
   // Start of virtual sequencer
     check_end_of_simulation
   // drop objection.

My virtual sequence has something like:


  scenario_id = 1;

  while(scenario_id <= 100) begin
    drive_seq_1();
    drive_seq_2();
    scenario_id++
  end

Now the problem is, after sending say, 20 scenarios the RTL hangs and the while loop never completes. That means I am never getting to the calling check_end_of_simulation() task in the test and the test runs forever.

How do I re-write my timeout mechanism to handle my requirement ? Are there any recommended ways of implementing requirements such as these, as pretty much all the verification environments need something similar to this ?

Thanks & Regards,
Madhu

2

MAdhu,

you may want to fork of your start of sequence and check_end_of_simulation in your test file.

3

A simple solution is to set set_drain_time and +UVM_TIMEOUT.

Sets the drain time on the given object.

set_drain_time ( uvm_object obj = null, time drain).

+UVM_TIMEOUT allows users to change the global timeout of the UVM framework. The timeout value is specified as an integer number of ns.

Syntax:


+UVM_TIMEOUT=<timeout>,<overridable> 

$$ vsim testbench +UVM_TIMEOUT=1000000,NO
4

In reply to Sushrut Veerapur:

Couple of recommendations:
• Use phase.raise_objection / phase.drop_objection inside a component’s phase methods to have that component participate in governing end-of-phase.
• Limit use of drain_time to uvm_top or the top-level test, if used at all.

5

Adding more thoughts:

UVM_HEARTBEAT monitor is very useful though underused,
I have not used it but already planned to use it since I am greatly impressed by reading about it.

I recommend you to read about before making any choice.