Doubt regarding UVM's RAL compared to OVM's RGM

UVM
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1

Hi,
I have a doubt related to UVM 's RAL with compared to OVM’s RGM. The OVM’s RGM seems to have only two sets of registers i.e., the actual ones belonging to DUT and the other belonging to the register model(testbench side regs to mimic duts regs). But the UVM’s RAL has three sets namely 1) DUT’s regs as usual and 2)Mirror registers 3)Desired value registers, the 2) and 3) are part of the testbench i.e., register model side. Why is this kind of implementation has been adopted in UVM RAL where as we could accomplish our tasks with the 2 sets as is in RGM. Can any one please enlighten me regarding the advantages or usecases related to this?
Thanks In advance.

Neith

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In reply to UVM Beginner:

Hi All,
Can anyone please share some knowledge regarding this query?

Thanks,
Neith

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In reply to UVM Beginner:

take a look at Tom Fitzpatrick’s Using the UVM register layer lesson in the advanced UVM course.
Desired value is the value you want to set. Only differences between desired and mirror values generate DUT (usually front door ) transactions. in a register sequence.

Hope this helps.