Do these examples assume that each stage of the pipeline only takes one clock cycle? - Please clarify

UVM
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This is related to the code examples given on Driver/Pipelined | Verification Academy

So as I understand it, the first sequence item begins with get(req) in the driver, and continues until it reaches the blocking command_phase(req) task in the BFM. One clock cycle of time will be consumed, and the next sequence item can begin and also reach this point. If the first stage of the pipeline is more than one clock cycle of simulation time, both threads will be running the first stage of the pipeline simultaneously, which doesn’t make sense. In these examples, is it assumed that each stage of the pipeline only consumes 1 clock cycle of simulation time?

Let me know if you need more clarification on my question, thanks.

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In reply to sdexter:

I see now that there is code in the tar example that shows the use of a READY signal to synchronize the pipeline stages.

My question now is, in the second example code where supposedly “item_done” is being used instead of put, there is no call to item_done. Is this missing, or is it not needed? Please clarify.