Creating parameterized sequence fail in uvm_registry.svh(67)

UVM
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1

Dear UVM experts,

while create a parameterized sequence object i run into this error (during Loading …):

Error: (vsim-7065) C:/modeltech64_10.5/win64/…/verilog_src/uvm-1.2/src/base/uvm_registry.svh(67): Illegal assignment to class mtiUvm.uvm_pkg::uvm_component from class work.simpleadder_pkg::simpleadder_sequence #(class work.simpleadder_pkg::simpleadder_transaction)

i tried casting just before assignment… but it seems that the error is within the create… in the return line 67.
i will appreciate any suggestion…
Y

the test class:
class simpleadder_test extends uvm_test;
typedef simpleadder_sequence#(.T(simpleadder_transaction)) sqce_t;
`uvm_component_utils(simpleadder_test)
…
function void simpleadder_test::build_phase(uvm_phase phase);
super.build_phase(phase);
sa_env = simpleadder_env::type_id::create( .name(“sa_env”), .parent(this) );
sa_seq = sqce_t::type_id::create( .name(“sa_seq”), .parent(this) );
endfunction: build_phase

endclass: simpleadder_test

the sequence class:
class simpleadder_sequence#(type T=uvm_object) extends uvm_sequence#(T);
`uvm_component_param_utils(simpleadder_sequence #(T))
…
endclass: simpleadder_sequence

the sequencer class:
class simpleadder_sequencer#(type T=uvm_object) extends uvm_sequencer #(T);
`uvm_component_param_utils(simpleadder_sequencer #(T))
…
endclass: simpleadder_sequencer

2

In reply to YN:

Your problem is here:
`uvm_component_param_utils(simpleadder_sequence #(T))
You are registering a sequence which is an object as acomponent. This is also what the error message is sayying.
Could you please explain why you are parameterizing your sequence with the same type as the seq_item is?

3

In reply to chr_sue:

Hi chr_sue,
Did the revised the sequencer to UN-PARAMETERIZED version. Still same error.
for your question: I generated parameterized agent which generates parameterized mon/drvr/sqcr.
At first stage when sequencer was without parameter it worked fine.
know even when going back… still same error… so my suspicion - its something else…
Y

4

In reply to YN:

did you have these changes as suggested by @chr_sue:
the sequence class:


class simpleadder_sequence#(type T=uvm_object) extends uvm_sequence#(T);
   
    `uvm_object_param_utils(simpleadder_sequence #(T))
     ...
endclass: simpleadder_sequence
5

In reply to voraravi:

Thank you voraravi, chr_sue,
I made the change… it works fine!
Thanks.
Y