CoverGroup Instantiation Issue!

UVM
1

Guys,

I have cover group declared outside of class and instantiated inside the class.

Getting “Segmentation Fault Issue” when I sample the same.


covergroup cg_axi (ref axi_transaction tr, input int addr_low, int addr_high );
option.per_instance = 1;
option.get_inst_coverage = 1;
option.merge_instances = 1;
cp_id			:	coverpoint tr.id		{
bins id[]	=	{[0:15]}; //0 to 15
}
cp_xact_type		:	coverpoint tr.xact_type{
bins wr	=	{axi_transaction::WRITE};
bins rd	=	{axi_transaction::READ};
}
cp_addr		:	coverpoint tr.addr	{
bins addr[10]	=	{[addr_low : addr_high]};
}
cp_blen		:	coverpoint tr.burst_length	{
bins blen[]	=	{[0:15]}; //1 to 16
}
cp_btype	:	coverpoint tr.burst_type	{
bins btype[]	=	{[0:2]}; //FIXED,INCR,WRAP
}
cp_bsize	:	coverpoint tr.burst_size	{
bins bsize[]	=	{[2:4]}; //32,64,128
}
endgroup

class fabric_scoreboard extends uvm_scoreboard;
...

axi_transaction cpu_slave_axi_tr,cpu_lpddr0_axi_tr,cpu_lpddr1_axi_tr,cpu_pcie0_axi_tr,cpu_pcie1_axi_tr,cpu_pcie2_axi_tr;

virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
cpu_slave_axi_tr= axi_transaction::type_id::create("cpu_slave_axi_tr");
cpu_lpddr0_axi_tr= axi_transaction::type_id::create("cpu_lpddr0_axi_tr");
cpu_lpddr1_axi_tr= axi_transaction::type_id::create("cpu_lpddr1_axi_tr");
cpu_pcie0_axi_tr= axi_transaction::type_id::create("cpu_pcie0_axi_tr");
cpu_pcie1_axi_tr= axi_transaction::type_id::create("cpu_pcie1_axi_tr");
cpu_pcie2_axi_tr= axi_transaction::type_id::create("cpu_pcie2_axi_tr");

//AXI
cg_axi_cpu_slave 		= new(cpu_slave_axi_tr,`AXI_CPU_SLAVE_ADDR_L,`AXI_CPU_SLAVE_ADDR_H);
cg_axi_cpu_lpddr0 	= new(cpu_lpddr0_axi_tr,`AXI_CPU_LPDDR0_ADDR_L,`AXI_CPU_LPDDR0_ADDR_H);
cg_axi_cpu_lpddr1 	= new(cpu_lpddr1_axi_tr,`AXI_CPU_LPDDR1_ADDR_L,`AXI_CPU_LPDDR1_ADDR_H);
cg_axi_cpu_pcie0 		= new(cpu_pcie0_axi_tr,`AXI_CPU_PCIE0_ADDR_L,`AXI_CPU_PCIE0_ADDR_H);
cg_axi_cpu_pcie1 		= new(cpu_pcie1_axi_tr,`AXI_CPU_PCIE1_ADDR_L,`AXI_CPU_PCIE1_ADDR_H);
cg_axi_cpu_pcie2 		= new(cpu_pcie2_axi_tr,`AXI_CPU_PCIE2_ADDR_L,`AXI_CPU_PCIE2_ADDR_H);

endfunction: build_phase

// AXI Slave write function
virtual function void write_axi_cpu_slave(axi_transaction tr);
axi_transaction local_tr;
local_tr = axi_transaction::type_id::create("local_tr");
local_tr.copy(tr);
case (tr.addr) inside
[`AXI_CPU_SLAVE_ADDR_L	:	`AXI_CPU_SLAVE_ADDR_H]	:	begin cpu_slave_axi_tr = local_tr; cg_axi_cpu_slave.sample(); end
[`AXI_CPU_LPDDR0_ADDR_L	:	`AXI_CPU_LPDDR0_ADDR_H]	:	begin cpu_lpddr0_axi_tr = local_tr; cg_axi_cpu_lpddr0.sample(); end
[`AXI_CPU_LPDDR1_ADDR_L	:	`AXI_CPU_LPDDR1_ADDR_H]	:	begin cpu_lpddr1_axi_tr = local_tr; cg_axi_cpu_lpddr1.sample(); end
[`AXI_CPU_PCIE0_ADDR_L	:	`AXI_CPU_PCIE0_ADDR_H]	:	begin cpu_pcie0_axi_tr = local_tr;  cg_axi_cpu_pcie0.sample(); end
[`AXI_CPU_PCIE1_ADDR_L	:	`AXI_CPU_PCIE1_ADDR_H]	:	begin cpu_pcie1_axi_tr = local_tr;  cg_axi_cpu_pcie1.sample(); end
[`AXI_CPU_PCIE2_ADDR_L	:	`AXI_CPU_PCIE2_ADDR_H]	:	begin cpu_pcie2_axi_tr = local_tr;  cg_axi_cpu_pcie2.sample(); end
endcase

endfunction: write_axi_cpu_slave

..

endclass

Please check and confirm that is there any issue on my code?

Thanks
John

2

In reply to John Verif:
Hard to confirm as there is a lot of missing code. Do you know that your write() method is getting a non-null tr? Also not sure what you are trying to do with local_tr. I think this could be simplified with


covergroup cg_axi (input int addr_low, int addr_high ) with function sample(axi_transaction tr);
// same body as above
endgroup

class fabric_scoreboard extends uvm_scoreboard;
...

cg_axi cg_axi_cpu_slave, ...; // you missed this

virtual function void build_phase(uvm_phase phase);
  super.build_phase(phase);
  
  //AXI
  cg_axi_cpu_slave 	= new(`AXI_CPU_SLAVE_ADDR_L,`AXI_CPU_SLAVE_ADDR_H);
  cg_axi_cpu_lpddr0 	= new(`AXI_CPU_LPDDR0_ADDR_L,`AXI_CPU_LPDDR0_ADDR_H);
  cg_axi_cpu_lpddr1 	= new(cpu_lpddr1_axi_tr,`AXI_CPU_LPDDR1_ADDR_L,`AXI_CPU_LPDDR1_ADDR_H);
  cg_axi_cpu_pcie0 	= new(`AXI_CPU_PCIE0_ADDR_L,`AXI_CPU_PCIE0_ADDR_H);
  cg_axi_cpu_pcie1 	= new(`AXI_CPU_PCIE1_ADDR_L,`AXI_CPU_PCIE1_ADDR_H);
  cg_axi_cpu_pcie2 	= new(`AXI_CPU_PCIE2_ADDR_L,`AXI_CPU_PCIE2_ADDR_H);
endfunction: build_phase
 
// AXI Slave write function
virtual function void write_axi_cpu_slave(axi_transaction tr);
  case (tr.addr) inside
   [`AXI_CPU_SLAVE_ADDR_L	:	`AXI_CPU_SLAVE_ADDR_H]	:	cg_axi_cpu_slave.sample(tr); 
   [`AXI_CPU_LPDDR0_ADDR_L	:	`AXI_CPU_LPDDR0_ADDR_H]	:	cg_axi_cpu_lpddr0.sample(tr);
   [`AXI_CPU_LPDDR1_ADDR_L	:	`AXI_CPU_LPDDR1_ADDR_H]	:	cg_axi_cpu_lpddr1.sample(tr);
   [`AXI_CPU_PCIE0_ADDR_L	:	`AXI_CPU_PCIE0_ADDR_H]	:	cg_axi_cpu_pcie0.sample(tr); 
   [`AXI_CPU_PCIE1_ADDR_L	:	`AXI_CPU_PCIE1_ADDR_H]	:	cg_axi_cpu_pcie1.sample(tr); 
   [`AXI_CPU_PCIE2_ADDR_L	:	`AXI_CPU_PCIE2_ADDR_H]	:	cg_axi_cpu_pcie2.sample(tr); 
  endcase
endfunction: write_axi_cpu_slave
 
..
 
endclass