I am referring to Vertically Integrated Environment Example
It discusses 3 possible choice of connecting user’s predictor component (a) AXI Master0 Port (b) AXI Slave Port (c) APB Agent
"In this example, there could also be up to three address translations taking place (AXI Master 0 to AXI Slave, AXI Master 1 to AXI Slave,
AXI Slave to APB) and the predictor used would need to use the right register model map
when making the call to predict() a target registers mirrored value."
Could someone elaborate on the the following statements ::
(A) “predictor used would need to use the right register model map when making the call to predict() a target registers mirrored value”
**(Q1) Is it related to address map ? .Wouldn't register / address map for AXI Master 0 and AXI Slave be the same ?**
**(Q2) How many register / address map exist for the environment ?**
Typically 1 map exists for each physical interface . My understanding is
1st map exists for AXI Master0 interface ,
2nd map exists for AXI Master 1 Interface ( although it uses sequences to send txns )
and a 3rd map would exist for APB interface ( reusing APB map at SOC level )
(B) “if the predictor is placed on the APB bus it will be able to verify that the correct
address mapping is being used for the APB peripheral and that bus transfers are behaving correctly end to end.”
**What does the following mean "correct address mapping is being used for the APB peripheral" ?**