I have an agent with producer and consumer components .
The producer has leaf1 component with uvm_blocking_put_port .
The consumer has leaf2 component with uvm_blocking_put_imp .
So typically the producer has uvm_blocking_put_port which leaf1’s blocking_put_port connects to and similarly
the consumer’s uvm_blocking_put_export would connect to leaf2’s uvm_blocking_put_imp .
What if I change producer’s port to export ? ( i.e uvm_blocking_put_export in parent which leaf1’s blocking_put_port would connect to )
I know that it results in a warning but I see that transaction does occur .
Will this be an Error for future versions ? Cos even with uvm-1.2 I simply see a warning
In reply to MICRO_91:
Can you show some example code, and specifically the warning message you are getting?
In reply to dave_59:
Hi Dave ,
class trans extends uvm_transaction;
rand int addr;
endclass
class leaf1 extends uvm_component;
`uvm_component_utils(leaf1)
uvm_blocking_put_port #(trans) out;
function new(string name, uvm_component parent=null);
super.new(name,parent);
out = new("out",this);
endfunction
virtual task run_phase(uvm_phase phase);
trans t;
phase.raise_objection(this, "prolonging run_phase");
t = new;
t.randomize();
out.put(t);
phase.drop_objection(this, "prolonging run_phase");
endtask
endclass
class comp1 extends uvm_component;
`uvm_component_utils(comp1)
uvm_blocking_put_export #(trans) out; // Changed from blocking_put_port TO blocking_put_export !!
leaf1 leaf;
function new(string name, uvm_component parent=null);
super.new(name,parent);
endfunction
virtual function void build_phase(uvm_phase phase);
out = new("out",this);
leaf = new("leaf1",this);
endfunction
// connect port to export one hierarchy Up !!
virtual function void connect_phase(uvm_phase phase);
leaf.out.connect(out);
endfunction
endclass
class leaf2 extends uvm_component;
`uvm_component_utils(leaf2)
uvm_blocking_put_imp #(trans,leaf2) in;
function new(string name, uvm_component parent=null);
super.new(name,parent);
in = new("in",this);
endfunction
virtual task put(trans t);
$display("Got trans: addr=%0d, data=%0d, write=%0d",t.addr, t.data, t.write);
endtask
endclass
class comp2 extends uvm_component;
`uvm_component_utils(comp2)
uvm_blocking_put_export #(trans) in;
leaf2 leaf;
function new(string name, uvm_component parent=null);
super.new(name,parent);
endfunction
virtual function void build_phase(uvm_phase phase);
in = new("in",this);
leaf = new("leaf2",this);
endfunction
// connect export to export
virtual function void connect_phase(uvm_phase phase);
in.connect(leaf.in);
endfunction
endclass
class env extends uvm_component;
`uvm_component_utils(comp1)
comp1 comp1_i;
comp2 comp2_i;
function new(string name, uvm_component parent=null);
super.new(name,parent);
endfunction
virtual function void build_phase(uvm_phase phase);
comp1_i = new("comp1",this);
comp2_i = new("comp2",this);
endfunction
// connect export to export at Same Hierarchy !!
virtual function void connect_phase(uvm_phase phase);
comp1_i.out.connect(comp2_i.in);
endfunction
endclass
initial begin
// Must set below for Warnings else No Warning !!
uvm_config_db#(uvm_bitstream_t)::set(null,"env*","check_connection_relationships",1);
e = new("env",null);
run_test();
end
Output is ::
UVM_INFO @ 0: reporter [RNTST] Running test …
**UVM_WARNING @ 0: env.comp1.leaf1.out [Connection Warning] env.comp1.out (of type uvm_blocking_put_export) is not at the same level of hierarchy as this port. A port-to-export connection takes the form component1.port.connect(component2.export)
UVM_WARNING @ 0: env.comp1.out [Connection Warning] env.comp2.in (of type uvm_blocking_put_export) is not down one level of hierarchy from this export. An export-to-export or export-to-imp connection takes the form parent_export.connect(child_component.child_export)
Got trans: addr=592721780, data=491544956, write=0
**