How do you check if an assertion has been triggered at the end of a test, if the assertion is within the RTL code?
In reply to VerifEx:
How do you check if an assertion has been triggered at the end of a test, if the assertion is within the RTL code?
Generally tools provide such information, including the number of time the assertions were pass and fail.
Tools generally have switches to provide such info.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
In reply to ben@SystemVerilog.us:
Is there a switch in VCS to enable this feature. I want a summary of how many times my assertions were triggered.
In reply to chr_sue:
A forum reminder:
Do NOT ask tool questions. Contact your tool vendor directly for support.