Can we run just testbench without DUT?

UVM
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1

Hi all,

I am running a testbench without DUT, But the interface outputs are connected as inputs to same testbench (like loop). Does this way simulation works or not??.
Because in my case, Time is not getting advanced, its staying at 0ns all the time and maximum iteration limit ERROR is shown.

2

Hi anilhr
It sounds like you have a combinatorial loop from one of the inputs, through the testbench, to the outputs, and back through the interface to the inputs again.

Is it easy to examine each of the input to output paths to identify those which are purely combinatorial? It sounds like one of the paths will be toggling between values in zero simulation time, causing an infinite loop.

For tricky loop problems I often use simulator performance profiling to identify which areas of code are being exercised repeatedly, and for one at time 0 you should also be able to single step through the code and see where it is looping.

But a quick analysis of the paths may prove quicker for you if the problem is a simple one to identify.
Richard

3

In reply to Richard Hamer (EnSilica):

Hi Richard,
Thanks for the info.

actually when i run test , even Build phase is not getting executed. Before going through any of the UVM phases this iteration limit error is coming.

4

In reply to anilhr:

Hi anilhr
I still think that could be consistent with combinatorial I/O loops. They are outside the scope of any UVM phasing.
Richard

5

In reply to Richard Hamer (EnSilica):

Hi Richard,

I have a doubt that does combinatorial loops exist in just testbenches, Because am not using any DUT to form combi loops.
If am wrong please correct me!.

And in fact i tried commenting those loop connections too.

Thank you,
anil