Can we pass signal reference through config_db?

UVM
,
1

Hi,

in testbench top i have one clock signal and i want to access that inside env class, thus i am planning to pass the clk signal reference through config_db.

tb_top →
wire clk;
uvm_config_db#(wire)::set(null,“*”,“clk”,clk);

is it possible?

Thanks,
Zalak Patel

2

In reply to zalak patel:

I would consider using an interface, and pass the interface to env instead.