Can I use uvm_hdl_read in a package file

UVM
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1

Hi,

I am trying to use uvm_hdl_read from inside a “test” file which is within a “package” file. But UVM doesn’t seem to like it and it’s giving me this error:

*ncvlog: E,ILLHIN (…/tests/reg_test_pkg.sv,165|51): illegal location for a hierarchical name (in a package).

So I changed the hierarchical reference of the actual top to “uvm_top”. But UVM threw another error:
*ncvlog: E,NOTCLM (…/tests/reg_test_pkg.sv,165|32): wrap is not a class item.

*here “wrap” is the instance name of my DUT in TOP.

Is there a way around this so I can “read” the hdl signal or port value from a testcase that is inside a package.

Thank you.

2

In reply to shamanth.h:

Ae does not know anything about the testbench hierarchy,i.e. you cannot pass them hierarchical path. It is simply a container which holds certain constructs and the scope is related to this package.