Can I build a UVM testbench with ModelSim PE Student Edition 10.1c?

UVM
1

I am trying to build a Open-Source UVM testbench for an Open-Source IP. By virtue of being a student, I have access to ModelSim PE Student Edition 10.1c.

So my question is, Can I build a SystemVerilog based UVM testbench with the ModelSim PE student Edition 10.1c?

2

Yes, but it would have to be very simple: no randomization or functional coverage.