Hi I have a UVM environment where a class looks at the transaction and does some modelling.
From this class, i want to call verilog code which also does some modelling in parallel. Both modelling are not related.
How to do this?
In reply to jyotsna:
Not sure what exactly you mean by the word “modeling” but I assume that some other Verilog code will need to be run.
The only mechanism that I am aware of is DPI-C. You will have to come up with “C” routines that can get called from your objects (say xyz_driver) and these “C” routines can in turn call a DPI-C exported task or function.
Hope this helps… but if you need more detail please provide more context
In reply to logie:
I’m not sure this needs to involve C code, but you definitely need to be clearer on what kind of Verilog code you need to call. If you mean tasks of a bus-functional model written in a verilog module, you can use the abstract/concrete class mechanism similar to what I wrote in my DVCon paper.
In reply to dave_59:
To give the context, i have a class which monitors the transaction and does some checks.
Some of these checks are present in verilog code also so i wanted to use these checks(remove duplicacy) and call them whenever a transaction is seen.
In reply to jyotsna:
If these checks are written ss Verilog tasks, then my DVCon paper outlines the approach you should take.
For some history, you might want to read OVM wrapper for Verilog Bfms?? | Verification Academy