Call backs

UVM
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1

Hi

I wrote a callback class to my driver component to make each transaction with a delay of 20 ns ,when I ran the simulation I got some compile errors i.e., class driver_callback is not a recognized class type .I am attaching the code link and the error message Please help me how to make my code compile free and implementation of callbacks

code link:

Error message:
Error-[SE] Syntax error
Following verilog source has syntax error :
Token ‘driver_callback’ not recognized as a type. Please check
whether it is misspelled, not visible/valid in the current context, or not
properly imported/exported. This is occurring in a context where a variable
declaration, a statement, or a sequence expression is expected. Either the
declaration type is not known or this is incorrect syntax.
“driver.sv”, 54 (expanding macro): token is ‘=’
`uvm_do_callbacks(freqdivbyn_driver,driver_callback,modify_pkt()); //
callback hook
^

#0, uvm_do_obj_callbacks(T=freqdivbyn_driver, CB=driver_callback, OBJ=this, METHOD=modify_pkt()) : “/apps/vcsmx/vcs/Q-2020.03-SP1-1//etc/uvm-1.2/src/macros/uvm_callback_defines.svh”:165
#1, uvm_do_callbacks(T=freqdivbyn_driver, CB=driver_callback, METHOD=modify_pkt()) : “/apps/vcsmx/vcs/Q-2020.03-SP1-1//etc/uvm-1.2/src/macros/uvm_callback_defines.svh”:140
full expansion of macro (uvm_do_callbacks), error at line 3
(* native_uvm *)begin
uvm_callback_iter#(freqdivbyn_driver,driver_callback) iter = new(this);
=> driver_callback cb = iter.first();
while(cb != null) begin
`uvm_cb_trace_noobj(cb,$sformatf(“Executing callback method ‘modify_pkt()’ for callback %s (driver_callback) from %s (freqdivbyn_driver)”,cb.get_name(), this.get_full_name()))
…

1 error
CPU time: 1.613 seconds to compile
Exit code expected: 0, received: 1

Thanks in advance
Harshavardhan

2

In reply to Harsha vardhan:

I see a different error message in your code.
You have a few weaknesses in your example around modport, clocking block and clk. If you are using a clocking block you do not synchronize on a clock edge!
And I do not understand why you are using the driver callback. It makes your example more complicated as needed.
But the key problem is uvm_callback is an extension of uvm_object.
For registering such a callback you have to use uvm_object_uitils instead of uvm_component_utils.
See here

3

In reply to chr_sue:

Hi

I changed the functions as per your suggestion but I am unable to run the callback test can you please help me with this.

I am Attaching the link for the code please look into it and let me know where the mistake is

code link:

Thanks in Advance
Harshavardhan

4

In reply to Harsha vardhan:

In errtest you have typo.
The callback type is:
derived_callback and not
derived_cb.
And you have an additional error in your environemnt line 28.
A uvm_error does not have a verbosity. It will be always displayed.
This line should be like this

`uvm_error(get_type_name(), "no config db object found")

See how it works here.

5

In reply to chr_sue:

Hi

I ran the code now I am getting other error i.e., Bad handle or reference.

and in my error test I given derived_callback only not derived_cb. My other doubt is when I am adding callbacks that line is showing errors can you please check.

When I am running main test I am not getting any errors when I am running err_test I am getting compile errors can you please check and help me

code link:

Error message:
UVM_INFO test.sv(25) @ 0: uvm_test_top [TEST] we are ending build phase of my test

UVM_INFO test.sv(26) @ 0: uvm_test_top [seq:body:config_db found] uvm_test_top

** Fatal: (SIGSEGV) Bad handle or reference.

Time: 0 ns Iteration: 10 Process: /uvm_pkg::uvm_phase::m_run_phases/fork#2213_7f5d6829eb7 File: /usr/share/questa/questasim/linux_x86_64/…/verilog_src/uvm-1.2/src/base/uvm_callback.svh

Fatal error in Function uvm_pkg/uvm_callbacks::add at /usr/share/questa/questasim/linux_x86_64/…/verilog_src/uvm-1.2/src/base/uvm_callback.svh line 590

HDL call sequence:

Stopped at /usr/share/questa/questasim/linux_x86_64/…/verilog_src/uvm-1.2/src/base/uvm_callback.svh 15 Function uvm_pkg/uvm_callbacks::add - -

called from /usr/share/questa/questasim/linux_x86_64/…/verilog_src/uvm-1.2/src/base/uvm_common_phases.svh 65 Function uvm_pkg/uvm_build_phase::exec_func - -

called from /usr/share/questa/questasim/linux_x86_64/…/verilog_src/uvm-1.2/src/base/uvm_topdown_phase.svh 111 Function uvm_pkg/uvm_topdown_phase::execute - -

called from /usr/share/questa/questasim/linux_x86_64/…/verilog_src/uvm-1.2/src/base/uvm_topdown_phase.svh 78 Function uvm_pkg/uvm_topdown_phase::traverse - -

called from /usr/share/questa/questasim/linux_x86_64/…/verilog_src/uvm-1.2/src/base/uvm_topdown_phase.svh 95 Function uvm_pkg/uvm_topdown_phase::traverse - -

called from /usr/share/questa/questasim/linux_x86_64/…/verilog_src/uvm-1.2/src/base/uvm_phase.svh 1390 Task uvm_pkg/uvm_phase::execute_phase - -

called from /usr/share/questa/questasim/linux_x86_64/…/verilog_src/uvm-1.2/src/base/uvm_phase.svh 2213 Task uvm_pkg/uvm_phase::m_run_phases - -

exit

End time: 06:14:09 on Jun 14,2022, Elapsed time: 0:00:04

Errors: 1, Warnings: 7

Done

Thanks in Advance
Harsha

6

In reply to Harsha vardhan:

The error message points you typically to a non-existing object. Please insert some more diagnostic messages to find out where it comes from.
I have identified your problem:
It comes from the build_phase of err_test:

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    `uvm_info(get_type_name(), "err_test build_phase", UVM_MEDIUM)
    drvd_cb = derived_callback::type_id::create("drvd_cb");
    `uvm_info(get_type_name(), "err_test build_phase here", UVM_MEDIUM)
    uvm_callbacks #(freqdivbyn_driver, dr_callback)::add(freqdivbyn_envrnmnt_h.freqdivbyn_agent_h.freqdivbyn_driver_h,drvd_cb);
    `uvm_info(get_type_name(), "leaving err_test build_phase", UVM_MEDIUM)
  endfunction

This is the line causing the problem:

dr_callback)::add(freqdivbyn_envrnmnt_h.freqdivbyn_agent_h.freqdivbyn_driver_h,drvd_cb);