Block level test bench integrate to system level verification

UVM
1

Hi ,

Please let me know
1. How a block level testbench in uvm can be integrated to system level testbench ?
2. How block level components and test cases are re-used at system level?

If there are some example code available please share the link.

Thanks ,
Kiran.P

2

In reply to kiranshrine:

See the UVM Cookbook.

3

In reply to kiranshrine:

Depending on the system, we like to reuse our reference models from the block tests in a larger context. We essentially stitch them together using the UVM analysis ports in the same order as the DUT. I have read all the literature, and there really isn’t an agreed upon way to do this- at least one that I find clean and reusable. We are actually revisiting it now.