Automatic bins for 15 bit register in UVM based register model

UVM
1

Hi All,

I have a 15-bit register in UVM based register model, to which I am writing 15’h7fff. The automatic bins getting generated for the register are as follows:

                            auto[0:8191]
                            auto[8192:16383]
                            auto[16384:24575]
                            auto[24576:32767]

In waveform, I can see 15 bits of register are getting written, but where as bins are concerned, out of these 4 bins, only 1 bin “auto[0:8191]” is getting hit.

Can anybody explain the reason for the same? Let me know, if need more details.

2

In reply to kmishra:

Could you please explain how your coverpoint looks like. If you let the simulator automatically generate the bins you get more then only 4 for a 15 bit variable.

3

In reply to chr_sue:

In reply to kmishra:
Could you please explain how your coverpoint looks like. If you let the simulator automatically generate the bins you get more then only 4 for a 15 bit variable.

What i understand is, since the bins got generated automatically from register model, it got broken bins into 4. 2 raise to power 15 is 32768. I am using vManager for coverage and to me, it’s showing these 4 bins only.

4

In reply to kmishra:

I do not see how you are sampling the covergroup. The issue might be there. The definition of your covergroup might be also of interest (including the sample method).