Followings are normal project phase for RTL simulation verification.
1)
1.1) Understand Design and do Test Plan / Feature Identification
1.2) Understand Design and start planning that what should be verification architecture for Design and what all interface and module xVCs.
2) Start implementation of 1.1 and 1.2
3) Debug failures
4) Target missing functional coverage (if any) and code coverage
Above steps and/or flow depend upon own experience and understating.
But Question is how much and what all are we can automate from above steps/ from typical verification phases ?
The flow that you mentioned is not quite correct because it missed the requirements phase.
Allow me to rephrase the flow as follows:
Traditional project phase for RTL simulation verification.
Understand the requirements and convert them into assertions and assumptions Note that an assertion is a statement about the correctness of the requirements,
and they can be expressed in an assertion language (e.g., SVA), or in
tables or algorithms (e.g., transformations of images), or in plain code
Define a verification plan based on the requirements, and not on the implementation of the design.
2.1) The verification plan will include methodologies to be used, such as formal verification, simulation, emulation with software.
2.2) If simulation, it will define a methodology, such as UVM, or UVM-like, sources of tests (e.g., constrained random tests, pre-processed data files, etc). Coverage is an important aspect here.
2.3) It will include the definition of tools that will expedite the process. Here, I am talking about simulators, emulation, tools that analyze coverage and tune the test vectors, debugging tools, and more.
2.4 RTL designers need to add assertions bound to the design because they Understand the Design and that would faciltate the debugging.
Start implementation
Debug failures
Target missing functional coverage (if any) and code coverage
Above steps and/or flow depend upon own experience and understating.
But Question is how much and what all are we can automate from above steps/ from typical verification phases ?
There are some automation tools. forma helps, also tools that link coverage with test vector generation.
I welcome comments from others.
Ben Cohen systemverilog.us