Can't we write assertions without clock reference?

UVM
1

Can’t we write assertions without clock reference?
I tried below code.
module i3c_assertion(scl,sda);
input scl,sda;
property i3c_start;
$fell(sda) |-> scl;
endproperty

assert property (i3c_start)
$display("start detected");
else $dispaly("start not detected");

endmodule

It gives error :“Could not determine the clocking event for ‘$fell’.”

Please help in solving this problem.

2

In reply to Vinodkr:

Property statement works on simulation ticks; that works on based on given clock or global clock or default clock. You didn’t put either.

3

In reply to sunils:

Assertions are working on sampling events and not on clocks. But we are using clock events as sampling events. A proper way is to use a clocking block for defining the sampling eventby


default clocking ....
endclocking

// write your properties and assertions here
4

I have 2 signals A and B.
A has to go LOW while B is already HIGH.
And there is no clock.
Is it possible to write assertion for this.

5

In reply to Vinod_KR:

As I said you can write properties/assertions for a unclocked/combinatorial design. Your assertions are evaluated with respect to sampling events. For this reason you need a sampling Event. This has to be regularly appearing signal like a clock.

6

Thanks for your reply.
But, sorry I didn’t understand clearly.
Can you please solve the above code for me.

Thanks.

7

In reply to Vinod_KR:

Please show your code structure. I don’t believe you have a completely combinatorial piece of code.

8

In reply to Vinod_KR:

Here you are finding an introduction regarding assertions:
https://www.doulos.com/knowhow/sysverilog/tutorial/assertions/

9

In reply to Vinod_KR:
sda is your reference “clock”

assert property (@negedge sda) sdl);

If sda falls and sdl change at the same timestep, you may have to the timing of those signals.