Architecture of an agent

UVM
1

Hi,
I need help in deciding the architecture for a agent . I have interface for my DUT which as cmd signals,cntrl signals,data signals.

The ctrl signals are independent of the cmd/data type signals. cmd and data signal are driven based on specific timing parameter(change as per clock speed ) like DDR interface . I dont have any responses for these transactions . So there is no out of order for this protocol. What kind of architecture do you think i need for this . Do i need to have separate sequences for each cmd,data lines and synchronize those sequence or i should generate one sequence item for both cmd/data and have logic in driver to obey timing parameters and drive dut (not a good way). What are my options .

Thanks

2

In reply to madcow:

I gues you have cm and related data. Correct?
If this is the case you need only 1 agent.
If your cmd-interface is doining some configuration of your DUT without needing related data from the data interface and vice versa you need a cmd agent and a data agent.

3

In reply to chr_sue:

In reply to madcow:
I gues you have cm and related data. Correct?
If this is the case you need only 1 agent.
If your cmd-interface is doining some configuration of your DUT without needing related data from the data interface and vice versa you need a cmd agent and a data agent.

Yes cmd and data are related . How do we maintain timing relationship between cmd/data should i do it driver or the sequence . I want driver to just drive the data not have any logic with timing between cmd/data . We need to tap into the signals of DUT ie clk period so that timing parameter are calculated for cmd/data timing . How to do we have this kind of logic in sequence .

4

In reply to madcow:

Any DUT related timing has to be implemented in the driver. The sequence does not know anything about clock cycles and control signals.
In the driver you have to implement the timing of your interface protocol. I guess you have to issue first the cmd and afterwards the data including possible control signalslike read_enable/write_enable cs etc.