Analysis port from example testbench

UVM
,
1

This is a snippet from UVM example testbench.
In the APB agent code snippet:

function void apb_agent::connect_phase(uvm_phase phase);
  m_monitor.APB = m_cfg.APB;
  m_monitor.apb_index = m_cfg.apb_index;
  ap = m_monitor.ap;
  // Only connect the driver and the sequencer if active
  if(m_cfg.active == UVM_ACTIVE) begin
    m_driver.seq_item_port.connect(m_sequencer.seq_item_export);
    m_driver.APB = m_cfg.APB;
  end
  if(m_cfg.has_functional_coverage) begin
    m_monitor.ap.connect(m_fcov_monitor.analysis_export);
  end

endfunction: connect_phase

I am not sure why analysis port in the agent is connected to monitor analysis port the following way:

 ap = m_monitor.ap;

Shouldn’t this be done using connect method?

2

In reply to verif_learner:

We cheated. ;-)

You must use the connect() method for connecting ports to exports, and we recommend using it for hierarchical port-port or export-export connections, as that is the easiest way to ensure reuse across arbitrary UVM testbench components. In the case of an agent, we know what the component architecture is, so we know that there is going to be an analysis_port in the monitor and it’s a bit more efficient to just assign it to the agent’s analysis_port.
In arbitrary UVM code, you can’t necessarily guarantee that the ports exist, so the assignment could fail if you’re not careful. The connect() method allows you to recover gracefully if there’s a problem.