Verification Academy

Search form

My Account Menu

  • Register
  • Log In
  • Topics
  • Courses
  • Forums
  • Patterns Library
  • Cookbooks
  • Events
  • More
  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • UVMF - One Bite at a Time
      • Introduction to UVM
      • Basic UVM
      • UVM Debug
      • Advanced UVM
      • UVM Connect

    • Featured Courses

      • Portable Stimulus Basics
      • Introduction to DO-254
      • SystemVerilog OOP for UVM Verification
      • Power Aware Verification
      • Power Aware CDC Verification
      • Assertion-Based Verification
      • Metrics in SoC Verification

    • Additional Courses

      • Clock-Domain Crossing Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal Coverage
      • Formal-Based Technology: Automatic Formal Solutions
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • UVM Forum

    • SystemVerilog Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • SystemVerilog Forum

    • Coverage Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • Coverage Forum

    • Additional Forums

      • Announcements
      • Downloads
      • AMS Forum
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizon - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • Correct Common RTL Issues - March 27th
      • Advance Your Verification Methodology - April 9th | Westford, MA
      • Low Power Verification Forum
      • Portable Simulus
      • Events Calendar

    • On Demand Seminars

      • UVM 1800.2 & Updated UVM Cookbook
      • Debug
      • FPGA Verification
      • Stimulus Generation
      • All On-Demand Seminars

    • Recording Archive

      • Portable Stimulus from IP to SoC
      • Wilson Research Group - 2018 Results
      • DAC & DVCon
      • UVM Forum
      • All Recordings

    • Mentor Training Center

      • SystemVerilog for Verification
      • SystemVerilog UVM
      • SystemVerilog UVM Advanced
      • Instructor-led Training

    • Mentor Learning Center

      • SystemVerilog Advanced OOP
      • UVM Transactions and Sequences
      • UVM Monitors and Agents
      • Functional Verification Library
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification Horizons Blog
      • Academy News
      • Technical Resources

    • Verification Horizons Publication

      • Verification Horizons - February 2019
      • Verification Horizons - November 2018
      • Verification Horizons - June 2018
      • Verification Horizons - March 2018
      • Issue Archive

    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Contact Us

    • Training

      • Questa® & ModelSim®
      • SystemVerilog
      • Functional Verification Library
Ask a Question
UVM
  • Home /
  • Forums /
  • UVM /
  • Analysis Export and Fifo in an uvm_object?

Analysis Export and Fifo in an uvm_object?

UVM 4395
analysis export 1 uvm_object 6 uvm_tlm_analysis_fifo 8
shamanth
shamanth
Forum Access
3 posts
January 03, 2019 at 2:02 am

Is it possible to add an analysis export and an analysis fifo in a class derived from an uvm_object?
Note: This class is not derived from uvm_component

Replies

Log In to Reply
dave_59
dave_59
Forum Moderator
6446 posts
January 03, 2019 at 1:16 pm

In reply to shamanth:

I don;t know if there is anything that forbids it, buut it would certainly be unconventional. Plus you lose the ability to debug TLM port connections (that might ultimately prevent it from compiling). You should try it and explain why think you need to do this.

shamanth
shamanth
Forum Access
3 posts
March 19, 2019 at 6:26 am

In reply to dave_59:

Hi Dave,

Thanks for reply.

1] Actually when we create an analysis port
analysis_port = new("analysis_port",this),
we pass "this" as the second argument. "this" needs the current instance to be a component. It throws error when the current instance is object.

2] If we don't pass "this" argument, then uvm error pop ups saying 2nd argument is missing (Where in it needs the current instance).

Regards
SHAMANTH HK

shimonc
shimonc
Full Access
18 posts
March 19, 2019 at 6:46 am

Did you try to put null instead of this?

chr_sue
chr_sue
Full Access
2020 posts
March 19, 2019 at 6:46 am

In reply to shamanth:

If you are looking to the source code you see the constructor ha 2 arguments:
function new (string name, uvm_component parent);

Because of this you cannot neglect the 2nd argument. But you could try 'null'.

Again it is not a good idea to implement an analysis port in an uvm_object.
Could you please explain what kind of object you are using?

shamanth
shamanth
Forum Access
3 posts
March 20, 2019 at 10:30 pm

In reply to shimonc:

Hi Shimonc,

Yeah i even tried that, but as it expects a valid component as argument compiler threw error saying it can't be null.

Regards
SHAMANTH HK

chr_sue
chr_sue
Full Access
2020 posts
March 21, 2019 at 12:16 am

In reply to shamanth:

When you want to implement a port/export in an uvm_object you need another object you want to connect these ports/exports to. But there is nothing.
If you want to send data from an object like a sequence to a component you can use uvm_events to do this.

© Mentor, a Siemens Business, All rights reserved www.mentor.com

Footer Menu

  • Sitemap
  • Terms & Conditions
  • Verification Horizons Blog
  • LinkedIn Group
SiteLock