About vip architecture in uvm

Can any one help me to understand what is vip in uvm? What is the difference between BFM and VIP ? How to implement a vip archirecture in uvm ? how the test bench looks like ,what is the flow?can we implement RAL in vip ?if yes how to integarte the RAL in test bench ,if no how we can access registers tb?

In reply to V P Haritha:

https://verificationacademy.com/forums/systemverilog/difference-between-bfm-vip-driver#reply-101405