Wrong result of div

SystemVerilog
, ,
4

In reply to saritr:

test.sv:


module test;

  bit signed [15:0]  rand_data_xi;
  logic [3:0] fact_log_2;

  bit signed [15:0] xi_prev  = 0;
  bit signed [15:0] yi_prev = 0;

  real ci_n;

  initial begin
    rand_data_xi = 16'hFFEE;
    xi_prev = 0;
    fact_log_2 = 4;
    ci_n =  (rand_data_xi - xi_prev) / (2 ** fact_log_2);
    $display("rand_data_xi = ", rand_data_xi);
    $display("2 ** fact_log_2 = ", 2 ** fact_log_2);
    $display("ci_n = ", ci_n);
  end

endmodule

qverilog test.sv:

rand_data_xi = -18

2 ** fact_log_2 = 16

ci_n = -1