Writing testcases for different frequency

SystemVerilog
1

Hi
I want to write testcases for different frequencies. But I’ve mentioned clock in TB top. Then how can I change frequency/time period according to different testcases?

2

Hi Neetu, One thing that comes to my mind is you can use a run time argument using

$value$plusargs

and according to your frequency expectation run tests conditionally.
@dave_59 is there any more optimized method?

3

What are you trying to verify by changing frequencies? There are different strategies based upon your verification goals.

4

Hi @cgales,

I have a design with about 5 different clocks, few of the clocks might be disabled under specific DUT conditions.

Which strategies could you suggest to be considered for a better verification of the design?
Are there any good papers to read on this topic?

Thanks

5

Treat the clock like stimulus. How to generate clock from the driver - #4 by dave_59