Writing SVA sequence involving a bus

SystemVerilog
,
2

In reply to lanfranco.salinari:

$rose(my_bus[0])[=1] intersect $rose(my_bus[1])[=1] intersect $rose(my_bus[2])[=1];
is same as
$rose(my_bus[0])&& $rose(my_bus[1])&& $rose(my_bus[2])[=1];
because you’re taking avout sequences of 1 cycle duration, at the sampling time.
How about something like the following:


bit [31:0] my_bus; 
sequence all_rose2; 
  $past(my_bus)==32'h0000_0000 &&  (my_bus)==32'hFFFF_FFFF; 
endsequence

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

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