In reply to ben@SystemVerilog.us:
Hi Ben,
what I had in mind when proposed “Having the possibility of looping in sequence and property definitions” was a very vague idea.
I understand that there could be a better way to write:
$rose(my_bus[0])[=1] intersect $rose(my_bus[1])[=1] intersect $rose(my_bus[2])[=1]
but I am not an expert of SV syntax, so I don’t know how this could be implemented.
The only thing that comes to my mind is having “sequence variables”, e.g.:
sequence s;
s = $rose(my_bus[0])[=1] intersect $rose(my_bus[1])[=1];
for (int i = 2; i < $size(my_bus); i++) begin
s = s intersect $rose(my_bus[i])[=1]
end
But I understand that all this should be made at compile time only, unless sequences and properties can be compiled “on the fly”, like regular expressions in, say, Python (I guess this would be slower).
In any case thanks for your availability.
Best regards,
Lanfranco