Writing an SVA assertion for detection of SOF(start of frame), EOF and checking for the zero data

SystemVerilog
7

Hi Ben,

I have run the code on EDA playground with Synopsys compiler. Following is the link to waveforms and the code (the only change at present is replacing detect with sync).

waveforms

code and log

It seems the ap_reset2sof: assert property is failing. Looks like problem with intersect operator. Intersect means both sequences start and end at the same time. However, when the SOF is being detected by frame_sof_eof.triggered[->1](second sequence), the ser_data will not be zero while the first sequence ser_data === 0)[*1:$] will expect data to be zero till second sequence completes. (Is my understanding correct?).
The property is failing as seen in the log.

regards,
-sunil