Writing an SVA assertion for detection of SOF(start of frame), EOF and checking for the zero data

SystemVerilog
5

Hi Ben,
thanks a lot for the code. I have done minor modifications to the code but I have some questions:


sequence frame_sof_eof;
      bit[11:0] sync; 
      @(posedge clk) (1, sync={ser_data, sync[10:0]}) ##0 detect==12'b111100001010; 
    endsequence

you have used detect variable but it is not declared anywhere. Should it be sync instead of detect?

Thanks again for the code.

regards,
-sunil