I have 2 interfaces , let’s call them valid and data. on the valid intf, valid can be set for 1 clk cycle. and at the same clk cycle , if data is sent (data is sent in a single cycle), it is considered a pass. If valid arrives and no data it is considered as a bug. If data arrives and no valid, it is considered as a bug as well.
Now, I have 2 uvm_analy_imp_decl ports _valid and _data. Either one of the write ports can get written to first. How can I create a simple check in my scoreboard to report pass or errors?