Create a Single thread that will verify user must first write the data to RAM before reading. ‘There must be at least single write request (wr) before the arrival of the read request (rd)’.Evaluate on positive edge of the clock.
someone please tell is it write
initial A2:assert property(@(posedge clk) !rd until $rose(wr) ##[1:$] $rose(rd))
$info("pass at %0t",$time);
else
$error("fail at %0t",$time);
These are property expressions:
The until is a property expression, it cannnot be followed by a sequence
initial A2:assert property(@(posedge clk) !rd until $rose(wr)) // ##[1:$] $rose(rd))
$info("pass at %0t",$time); else $error("fail at %0t",$time);
// But there still is an issue as it does not address the mem addr
From my SVA book, /ch10/10.15/memory_data_integrity_check.sv
module memory_data_integrity_check (
input bit write, // memory write
input bit read, // memory read
input bit[31:0] wdata, // data written to memory
output bit [31:0] rddata, // ** NEW: data read from memory
input bit[31:0] addr, // memory address -- small for simulation
input bit reset_n, // active low reset
input bit clk); // clock
timeunit 1ns; timeprecision 100ps;
default clocking cb_clk @ (posedge clk); endclocking
int mem_aarray[*]; // associative array (AA) to be used by property
bit [31:0] raadata; // data read from AA
bit mem_aarray_exists; // exists at specified address
assign mem_aarray_exists = mem_aarray.exists(addr);
always_comb begin
if(mem_aarray_exists)
raadata = mem_aarray[addr];
rddata= raadata;
end //
always@ (posedge clk)
if (reset_n==1'b0) mem_aarray.delete; // Clears AA elements
else if (write) mem_aarray[addr] = wdata; // store data
// If a write, save addr into v_wraddr, save data write into v_wraadata
// if at some time we have a read, and the address exists in the associative array
// and the address is the one used in a previous write then
// the IO eddata==what was previously written
property p_read_after_write;
bit [31:0] v_wraadata, v_wraddr;
(write, v_wraddr=addr, v_wraadata= wdata) |-> // if write, save data and addr
(read && mem_aarray_exists && addr==v_wraddr) [->1] ##0 // @read and data there at same written addr
//(read && mem_aarray.exists(addr) && addr==v_wraddr) [->1] |-> // @read and data there at same written addr
rddata==v_wraadata; // *** read data from IO is same as what was written
endproperty : p_read_after_write
ap_read_after_write : assert property (p_read_after_write)
$info("addr =%h, raadata=%h", $sampled(addr), $sampled(raadata)); else
$error("addr =%h, raadata=%h", $sampled(addr), $sampled(raadata));
property p_read_before_write;
not (read && !mem_aarray_exists); // never a read on an non written address
endproperty : p_read_before_write
ap_read_before_write : assert property (p_read_before_write);
endmodule : memory_data_integrity_check
// *** Testbench needs to be updated, it is not correct
class c_xactn;
rand bit write; // memory write
rand bit read; // memory read
rand int wdata; // data written to memory
rand bit[31:0] addr; // memory address
constraint addr_range_cst { addr <= 4 ; wdata <=3; wdata >=0; }
constraint no_wr_and_rd_cst { !(read && write);}
endclass : c_xactn
module top;
timeunit 1ns; timeprecision 100ps;
bit write; // memory write
bit read; // memory read
int wdata; // data written to memory
int rddata; // data read from memory
bit[31:0] addr; // memory address
bit reset_n=1'b1; // active low reset
bit clk=1'b1; // clock
c_xactn c1=new();
memory_data_integrity_check mem_check1 (.*);
initial forever #50 clk=!clk;
always_ff @ (posedge clk) begin
if(!c1.randomize()) $error("c1 randomization failure");
write <= c1.write;
read <= c1.read;
wdata <= c1.wdata;
addr <= c1.addr;
end
initial begin
bit v_a, v_b, v_err;
repeat (200) begin
@(posedge clk);
if (!randomize(v_a, v_b, v_err) with {
v_a dist {1'b1 := 1, 1'b0 := 1};
v_b dist {1'b1 := 1, 1'b0 := 2};
v_err dist {1'b1 := 1, 1'b0 := 15};
}) `uvm_error("MYERR", "This is a randomize error");
a <= v_a;
if(v_err==0) b<=v_b; else b<=!v_b;
end
$finish;
end
endmodule : top
thank u so much for your reply,i just started learning assertions .
can u recommend me any source to learn assertions for beginner level.