Write a constraint to generate a random number with only 5 bits set and consecutively set for 80% of the time

SystemVerilog
1

Constraint Question : Write a constraint to generate a random number with only 5 bits set and consecutively set for 80% of the time.

My solution: Fix the number of set bits and as soon as you see a set bit, AND the next 5 bits and use the dist keyword for the probability. Is this the best approach to solve this question?

class sample;
  rand bit  [31:0] x;
  
  constraint c{
    $countones(x) == 5; 
  
  foreach(x[i]){
    if(x[i] && i<28){
      (x[i]&&x[i+1]&&x[i+2]&&x[i+3]&&x[i+4]) dist {1:=80,0:=20};  
    }
  }
    
  }
endclass

module tb;
  
  sample s = new();
  initial begin
    repeat(10) begin
      s.randomize();
      $display("%b",s.x);
    end
  end
  
endmodule
2 
class a;
  rand bit[31:0] var1;
  rand bit set_consctv;
  rand int N;
  constraint c_var1{
    $countones(var1) == 5;
    N inside {[0:27]};
    if (set_consctv)
      var1 == 5'b11111 << N;
    else
      foreach(var1[i])
        i <=27 -> var1 != 5'b11111 << N;
  }
          constraint c_set_consctv{
            set_consctv dist {1:=80, 0:=20};
          }
endclass