Write a checker

SystemVerilog
1

I need to write a checker in below actual snippet code

Task
Repeat(1) @posedge clk
Ld=1;
Repeat(4)@posedge clk
Ld=0;
Endtask

After 4 clks means at 5th clk load is becoming zero, but due to flop delay, 1 delay it should shift and at 6th clk it should be zero but its not happening for 1 case, so i need to write checker at 5th clk whether ld is zero or not and make make ld zero at 6th clk

2

Rather than showing us a hand written picture, pleas write a complete example that generates the stimulus you want to check that should pass and fail.