Working with multi-dimensional associative arrays

SystemVerilog
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3

In reply to dave_59:

Hi Dave,

This is the error I got from my compiler,
Assignment pattern - LHS must be an array or structure [SystemVerilog]. (Probably because it might not support latest SV constructs)

Also, I was trying something on www.edaplayground.com/

module integer_associative_array ();

  int  ARY[*][*] = 
'{
  "A19" : '{0:'{0,1,2,3} , 1:'{4,5,6,7}},
  "A33" : '{30:'{1,6,5,7} , 31:'{8,9,10,11}}
};
  
  initial begin
    
    $display ("value stored is %p", ARY["A19"][0]);
    
  end
  
endmodule

This gives me the following error, Error: testbench.sv(8): Illegal assignment pattern. The number of elements (4) doesn’t match with the type’s width (32).

Shouldn’t ARY[“A19”][0] return this array - {0,1,2,3} ?
Am I missing something?
Thank you