In reply to Frank.Wang:
The factory relies on static variable declaration initialization inside your class to populate an array in the UVM package. This static variable is inside the uvm_object_registry class, which gets added by the `uvm_object_utils macro.
The question becomes: ‘If I compile a package, but never import it, does it exist?’ There is a similar question with compiling libraries of modules and only some of them are instantiated. The LRM does not address these issues See 0002511: what constitutes a sufficient reference to a package to cause it to be elaborated into a design? - Accellera Mantis.
Fortunately, most tools have fairly consistent ways of dealing with this.
At one extreme there is the single step compile everything and simulate everything I compiled. At the other extreme there is the separate compile where every file is compiled in separate steps into a work library. Then in simulation, you provide the top level modules and packages you want, then the tools brings in (elaborates) only the design units it needs to run the simulation.