Wildcard import

SystemVerilog
2

In reply to SidRaj:

package p;
  bit a,b,c,d;
endpackage
module top;
  wire w,x,y,z;

  import p::a; // explicit import of a
  import p::*; // wilcard import of p. identifers b,c,d are all candidates.
  
  assign x = a; // referes to p::a, it was explicitly imported
  assign y = b; // p::b is now imported
  bit c;  //       p::c is no longer a candidate for import
  // declaring a or b here would be an error since they have already been imported
  // declaring d here would override the wildcard import
  // since we never declarted or referenced d, it is not imported
endmodule