Why this code not producing the desired result for the given question- "Constraint to generate 0, 1, x and z randomly"

SystemVerilog
1 
class abc;
  rand logic a;
  
  constraint cons1 { a inside {0,1,x,z};};
  
endclass 

module abc;
  abc a1;
  
  initial begin
    a1=new();
    repeat(10) begin
    	a1.randomize();
      	$display("%d",a1.a);
    end
  end
endmodule
2

You can’t use 4-state values when randomizing. You need to use an intermediate variable with a post_randomize() function:

class abc;
  
  rand int a_int;
  logic a;
  
  constraint cons1 { a_int inside {[0:3]};};
  
  function void post_randomize();
    case(a_int)
      0: a = 0;
      1: a = 1;
      2: a = 'x;
      3: a = 'z;
    endcase
  endfunction
  
endclass 

module abc;
  abc a1;
  
  initial begin
    a1=new();
    repeat(10) begin
      if (!a1.randomize()) begin
        $display("Randomization failed");
      end
      else begin
        $display("%b",a1.a);
      end
    end
  end
endmodule