Why phase raise_objection and drop_objection is required in test class run_phase?

In reply to Subhra Bera:
You are mixing 2 things together:
(1) the interface between sequencer and driver
(2) the objection mechanism.

The objection mechanism is used to stop the simulation after all components in your UVM environment are ready with their work.

For the handshake between sequencer and driver there are 2 different approaches possible:
(1) get/put, this TLM 1.0 style
(2) get_next_item/item_done this is TLM 2.0 style