In reply to ben@SystemVerilog.us:
Typically, one uses clocking events. The following works, regardless of the order of the blocks in the fork-join
module tb;
bit clk;
initial forever #10 clk=!clk;
task automatic my_first_task (input logic [31:0] addr, ref logic [31:0] data);
@(posedge clk);
data = 8'h2; // non-blocking assignment may not be an automatic variable
for (int i=0; i <1; i++) begin
$display ("@ %t Entering the loop ", $realtime);
end
for (int i=0; i <1; i++) begin
$display ("Entering the second loop");
end
endtask
logic [31:0] addr, data;
initial begin
data = 'h10;
addr = 'h01;
fork
begin
// @(posedge clk);
@ (data);
$display ("@ %t Read from bus %h \n", $realtime, data);
end
my_first_task (addr,data);
join
end
endmodule
# @ 10 Entering the loop
# Entering the second loop
# @ 10 Read from bus 00000002
#
****NOTE
The following has a race condition
module tb;
bit clk;
initial forever #10 clk=!clk;
task automatic my_first_task (input logic [31:0] addr, ref logic [31:0] data);
@(posedge clk);
data = 8'h2; // non-blocking assignment may not be an automatic variable
for (int i=0; i <1; i++) begin
$display ("@ %t Entering the loop ", $realtime);
end
for (int i=0; i <1; i++) begin
$display ("Entering the second loop");
end
endtask
logic [31:0] addr, data;
initial begin
data = 'h10;
addr = 'h01;
fork
begin
@(posedge clk);
$display ("@ %t Before the @data %h \n", $realtime, data);
@ (data); // <<< Gets bloked here, waiting for a new change
$display ("@ %t Read from bus %h \n", $realtime, data);
end
my_first_task (addr,data);
join
$display ("@ %t After the joins %h \n", $realtime, data);
end
endmodule
@ 10 Entering the loop
# Entering the second loop
# @ 10 Before the @data 00000002
WIth the #1 as in
@(posedge clk); #1;
data = 8'h2;
It WORKS OK
@ 10 Before the @data 00000010
#
# @ 11 Entering the loop
# Entering the second loop
# @ 11 Read from bus 00000002
#
# @ 11 After the joins 00000002
#
BTW, this forum does not discuss tools. One should ever identify the tool you are using. You can just say “my tool deos this”, but in the this, delete anything that can identify the tool. Your question is Not a tool issue, but a SystemVerilog issue.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- SVA Alternative for Complex Assertions
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