In reply to njain:
Your assumptions about the predictor or more accurate your refenece model are wrong.
The prdictor/refence model is a TL model and it is completely independent of any timimg. It does not know anything about clock cycles and control signals. It has only 1 odering scheme. This is the order of data. Your RTL model is very specific and dependent on clock cycles and contrl signals. Beside of these signals it has also data signals like addresses and data. They will be extracted from a monitor. This is what you have to compare against the data of your reference model. The exact protocol of your functional interface can be checked using SV assertions. This checks the right timing behavior.