Why i am getting output as a=0, b=0 and c=0, in below posted system verilog code?

In reply to swapnilsrf9:

Please modify width of a to 6, because when b = 13 & c = 9, a is constrained to (b + c), according to your constraint adjusted to 4 bits.

i,e b = 4’b1101b & c = 4’b1001. So, when you add b & c, you will get 10110b, but since a is only 4 bits, the higher bits are truncated. So, you may be getting a as 6 for this randomisation. Am I correct???

Changing a to rand int, or rand bit [5:0] might solve…